Hosted by Condor Computing · 🇺🇸 US · EN · 43 episodes
Established thought leaders with verified media credentials.
Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.
Condor Computing hosts Condor Currents, a technology show with 43 episodes published.
## Episode Summary In this episode, we cover: - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History
## Episode Summary In this episode, we cover: - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern So
## Episode Summary In this episode, we cover: - **Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU wi
## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **Nvid
## Episode Summary In this episode, we cover: - **Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **Observation, Not Prediction: Conversation-Lev
## Episode Summary In this episode, we cover: - **FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling** (arXiv) - **Code size reduction by advanced
## Episode Summary In this episode, we cover: - **Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory** (arXiv) - **Code size reduction by advanced near addressing modes
## Episode Summary In this episode, we cover: - **Sustainable Real-Time 8K60 HEVC Encoding for V2X: Repurposing Legacy NVENC Hardware at the Vehicular Edge** (arXiv) - **PoisonCap: Efficient Hierarchical Temporal Safety
## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardwa
## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardwa
## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardwa
## Episode Summary In this episode, we cover: - **OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization** (arXiv) - **TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing**
## Episode Summary In this episode, we cover: - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 -
## Episode Summary In this episode, we cover: - **Enhancing Instruction Prefetching via Cache and TLB Management** (arXiv) - **ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses** (arXiv) -
## Episode Summary In this episode, we cover: - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Nvidia's CUDA platform now supports RISC-V — support brings
## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **The
## Episode Summary In this episode, we cover: - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe** (google_riscv) - **Checking In On The ISA Wars And Its Impact On CPU Archi
## Episode Summary In this episode, we cover: - **SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison** (arXiv) - **Beyond Static Policies: Exploring Dynamic Policy Selection for Single-Thread
## Episode Summary In this episode, we cover: - **RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures** (arXiv) - **SPEC CPU2026: Characterization, Representati
## Episode Summary In this episode, we cover: - **Optimizing Branch Predictor for Graph Applications** (arXiv) - **A Comparative Analysis of ARM and x86-64 Laptop-Class Processors: Architecture, Assembly-Level Performanc
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Condor Currents is hosted by Condor Computing. The show is categorised under technology (news) and has published 43 episodes.
Condor Currents has published 43 episodes.
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